AMD will bet on the acceleration AI in future chips
According to a recent interview with the technology officer of AMD Mark Papermaster (Mark Papermaster) reporters EETimes, AMD is going to join the race of accelerators task deep learning on the client and embedded systems. However, the company is not yet ready to provide any details in this regard for its 7-nanometer chips Ryzen 2 x86 and GPU Vega/Navi, which it intends to promote over the next year, and plans after 7 nm.
“There is a need for high performance with what we call edge
At the end of 2016, AMD has released the first GPU-accelerators for tasks deep learning in data centers. Ever since Google TensorFlow Processing Unit and other specialized projects have demonstrated the benefits of adding arrays of blocks multiply-add (multiply-accumulate, MAC) in hardware to accelerate algorithms in deep learning.
In may 2017 the basic competitor AMD in the graphics field NVIDIA, introduced the Volta architecture is the first GPU with built-in MAC blocks, which are called nuclei tensor (tensor cores). Intel also said this year that it plans to add your accelerator Movidius on the motherboard of a PC running Windows ML. Analysts believe that Intel eventually will add in a normal desktop processors kernel-based Movidius.
Mr. Papermaster not say whether AMD is planning to integrate MAC-arrays of 7-nanometer boosters Vega, which will hit the market later this year or x86 processors Zen 2, now scheduled for early next year. However, he noted that Vega will support additional formats in addition to 16-bit instruction floating point who are supporting graphics accelerators company. In the IT industry is busy discussing ways to simplify neural networks to speed up tasks deep learning. ARM will support 8-bit operations on their ML Core, NVIDIA examines the prospects of two-bit operations, and Imec is one bit alternative.
Yet public AMD plans apply only to products Zen 3, which will be produced using a 7-nm EUV-process technology (lithography in the extreme ultraviolet range), probably starting in 2020. Mr. Papermaster declined to comment on future plans.
Contract manufacturers have already started to learn a 5-nm and are looking for investors for a 3-nm process technology. “Semiconductor factories to increase performance efficiency per watt and density of transistors, but the process has been steadily slowing down compared to the traditional pace of “Moore’s Law”, to which industry is accustomed. …We will use a complete new workflows in the order of their development. …In addition, we have a heterogeneous approach in the use to speed up the computations the CPU, GPU and other cores on a single chip,” said mark Papermaster.
AMD also expects to take advantage of so-called packaging chips 2.1 D, which are used in smartphones and could be useful to improve a powerful PC and server chips. Last year Mr. Papermaster said that such options will become available in two to three years. But this year they look, unfortunately, slightly closer.
“We see that OSAT companies use new methods, he said. Packaging 2.5 D have proven to be promising, and experiments with other methods of layered host crystals will begin to bear fruit over time …I think we will see alternative packaging 2.5 D in the next few years.” Recall: AMD has increased the pressure on NVIDIA in 2015, releasing a graphics accelerator Fiji with HBM memory in the package 2.5 D. But this method was relatively expensive and still not suitable for the mass market like a game of cards.
Mark Papermaster did not want to dwell on the progress of the joint venture by AMD with the Chinese Tianjin Haiguang Advanced Technology Investment on production server x86 processors based on the architecture of Zen. Briefly noted: “just as AMD Ryzen and EPYC were well received by the market, I think that x86-products of our joint venture will be in demand. There is a huge install base, so the barrier to entry to the market is minimal.”